Synchronous digital communication systems are well known in the art. In such systems, it is known to transmit a synchronization signal either as a preamble or postamble to a data signal, or periodically interleaved within a data message. Receivers operating within these systems must correctly locate and decode the synchronization signal to properly receive the data message.
Prior synchronization schemes have employed fixed length predetermined digital patterns that are stored in the receiver in some convenient memory means. The incoming data stream is compared bit-by-bit to the predetermined digital sequence until the sequence is located and correctly decoded. However, this seemingly simple task is complicated when errors are introduced into the received data stream due to noise, signal path fading, and other adverse signal phenomena. Accordingly, some radio receiver designers have simply relaxed the criteria for detection of the synchronization sequence (for example 13 out of 15 bits). Other receiver designers, desirous of maintaining the higher standard of 100% correlation, have employed error correction means to correct erroneous bits prior to the synchronization detector.
In a secure communication system, the fixed length predetermined synchronization signal is impractical since the goal of a secure communication system is to transmit a bit stream that appears random in nature. Placing a predetermined fixed length synchronization pattern within an encrypted message may compromise the security of the system in that an unauthorized receiver may "focus" on the repeated pattern and extract the encoded data in an attempt to break the particular encryption algorithm employed. Additionally, the fixed length synchronization sequence adds "overhead" to the synchronization process. Therefore, a need exists to provide a reliable synchronization detector that may be used in a synchronization system suitable for a secure communication system.